1. Field of the Invention
This invention relates generally to a method for fabrication of shallow trench isolation. More specifically, this invention relates to a method of compensating for the difference in dielectric thickness between narrow trenches and wide trenches.
2. Description of the Related Art
The most important factor that ensures the quality of shallow trench isolation is the dielectric used for isolation and its uniformity across multiple trenches. Circuit design considerations will frequently require varying trench widths. There is a need for a cost-effective process to fill these trenches of varying widths with a dielectric of uniform thickness.
One current method is to fill the trenches with oxide using CVD. The resulting gap-fill oxide layer is then planarized using CMP as is well known by one skilled in the art. The problem with this process is that the oxide layer will be polished at a higher rate in wide trenches resulting in the phenomenon known as "dishing." The dielectric thickness in wide trenches will be less than the dielectric thickness in narrow trenches resulting in a different capacitance and a faster device deterioration.
Another current method of fabricating shallow trench isolation is to use a photoresist mask inverse to the structured layer to be planarized then back-etch as is disclosed by U.S. Pat. No. 5,212,114 (Grewal et al.). The problem with this method is that the added steps of inverse masking and back-etching are difficult and expensive.
U.S. Pat. No. 5,453,639 (Cronin et al.) discloses a planarization processcomprising oxidizing Si particles and CMP.
U.S. Pat. No. 5,346,584 (Nasr et al.) discloses a method of planarizing an isolation using a polysilicon layer that is oxidized.
U.S. Pat. No. 5,643,836 (Meister et al.) discloses a planarizing method using etch back techniques.
The closest and aparently more relevant technical developments in the patent literature can be gleaned by considering the aforementioned patents.